Instructional Objectives
To learn how to implement simple logic functionsusing
discrete 74HC-series components.
To learn how to use Boolean algebraic simplificationto
change a circuit’s realization.
To see a motivating reason to learn more circuitminimization and mapping techniques that can beused to
improve the

• Your lab points are contingent on completion of thesesteps.
For this lab, you will need your lab kit and AD2, andyou may find it helpful to install the KiCAD softwaresuite on your own computer to use Eeschema athome. You will build the circuit you describe in theprelab, and you will verify its operation with Autolab.
In the prelab, fill out the truth table for the followingBoolean function(s), convert them to NAND-NAND andNOR-NOR
versions, ands draw a schematic using onlyinverters, 2-input
NOR, 2-input NAND, 3-input NAND, anda 2-input AND gates in Eeschema.

F1(W,X,Y,Z) =
X·Z’ + W’·X + W’·Y + Y·Z’
F2(W,X,Y,Z) =
(X’·Y’)’ · (W·Z)’
With the help of your prelab schematic, you will build
theactual circuit, again using only the aforementioned gates.
Your circuit must be ready to test by the time youarrive at your lab section. Building and debuggingcan take an inordinate amount of time, and preventyou from finishing the lab.
Step 0: Prelab
entire
lab document, including Steps 0.xbelow.
Do the
prelab
assignment
on the course web page.
Build the circuit from your schematic
before

Step 0.1: Evaluate the Truth Table forF1(W,X,Y,Z) and F2(W,X,Y,Z)
Fill in the truth table for F1(W,X,Y,Z) and F2(W,X,Y,Z) inthe
prelab submission. These Boolean functions arelogically
equivalent, so either one can be used to build thetruth table.
The other can be used to check itscorrectness.
Step 0.2: Convert F1 to a NAND-NANDimplementation

Use DeMorgan’s Law to convert F1 into an expressionthat can be
implemented by four 2-input NAND gates anda 4-input NAND gate.
Step 0.3: Convert F2 to a NOR-NORimplementation
Use DeMorgan’s Law to convert F2 into an expressionthat can be
implemented by three 2-input NOR gates.
Step 0.4: Schematic of F1 and F2
Implement the converted NAND-NAND and NOR-NORfunctions as a schematic in Eeschema, and submit it inthe prelab submission. Your schematic must present adetailed plan of how you will use the chips in your kit toimplement the circuit. In particular, you must ensure thefollowing:
Each gate symbol must clearly indicate which pinnumbers it will use. You must change the Unit on thegate symbol so that the pin numbers are not thesame for different gate symbols.
Each gate symbol must be labeled as Unx, where ‘n’is a number to indicate that it belongs to a specificchip, and ‘x’ is the Unit of the gate symbol. Forexample, if you add four 74HC00 gate symbols, andyou intend to use all four of them on the same74HC00 chip, you must label them as U1A, U1B,U1C and U1D respectively. For U1A, the pins wouldbe 1,2 and 3. For U1B, the pins would be numbered4,5,6, and so on. The symbols should look like
Subschematic 1
below.

For the 74HC10 and 74HC08, you may need to use74LS10 and 74LS08 since the HC versions do notexist in the Eeschema symbol libraries. The chipnumbers should still match.
You must specify the inputs with the Label option,which can be accessed by pressing the L key orgoing to Place > Label in the top bar.
Your schematic must be clean and orderly. All addedwires must be useful, i.e. connected between twocomponents, not placed without purpose. Allcomponents must be labeled with the Unx format asspecified above, and be of the correct type. Thelabels used for gate inputs W, X, Y and Z must beeasily readable.
For the 4-input NAND gate, you may choose one oftwo options:
Use one gate of a 74HC10 3-input NAND gateand one
gate of a 74HC08 AND gate. This isprobably the
easiest to understand, although itrequires the
addition of an extra chip to producethe intermediate
result. (
Subschematic 2
)
Use all three gates of a 74HC10 triple 3-inputNAND gate
chip. (
Subschematic 3
) Use one ofthe gates as an inverter by wiring all three inputstogether or connecting two of the inputs to V
CC
.That “inverter” is used to invert the
output ofanother 3-input NAND gate to form a 3-inputAND gate. Only two inputs of this “3-input ANDgate”
will be used. The third input should eitherbe
connected to V
CC
or redundantly connectedto
one of the other inputs. An input for a gatewhose
output is being used should never be left

unconnected.
An unconnected input is notalways low. It will float
unpredictably betweenhigh and low states and cause you
greatpuzzlement.

These alternatives are typical ones you wouldconsider if
you were creating a real device, sothinking about how you
want to do them is a realisticexercise. There are two
considerations to keep inmind:
1.
Using a 2-input AND gate will mean adding anextra chip
power consumption and spacerequirements.
2.
Using two 3-input NAND gates to build a 2-inputAND gate
will result in a slower gate than using a74HC08 AND
gate. (A 74HC10 has a longerpropagation delay than a
74HC08, and it takestwo of these gates. The result is
more than twiceas slow as a 74HC08 AND gate.)
There is no 4-input NAND gate in your lab kit, soimplement it
using a 3-input NAND gate for which one ofits inputs is a 2-input
AND gate. All four of the 2-inputNAND gate outputs can then be
accommodated. The twoNAND gate outputs to connect to the AND gate
should bethose that combine the W’/X and X/Z’ signals. Those arethe last two terms in the F1 function. From the standpointof logical
equivalence, it does not matter which NANDoutputs are connected to
the AND inputs. We want tospecifically connect these two NAND gates
to the ANDgates to have a predictable timing model.

Ensure that your schematic follows the design rulesoutlined above, and upload your schematic file to theprelab. Failure to follow directions will cost youpoints.

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